Kirsch Handbook

Development

  • CHERI RISC-V Cheatsheet
  • Kirsch Coding Style
  • Methodology
  • Morello Curiosities

Design

  • Cheriette
  • Cheriette Development and Debugging
  • Example design of some subsystem
  • Exception Levels
  • The global logical address space
  • Interrupt Handling
  • Related work
  • Secure Calls
  • Tasks

Tutorials

  • Acquiring the Kirsch Toolchain
  • Building Kirsch
  • Executing Kirsch
  • Build system
  • Souce Structure
  • Writing specifications in Sockeye3
  • seL4 in GLAS
Kirsch Handbook
  • Related work
  • View page source

Related work

  • CheriOS: Thesis from Lawrence G. Esswood with the original CHERI folks. The first OS for CHERI designed from the ground up.

  • CompartOS: Thesis from Hesham Almatary, with the original CHERI folks. FreeRTOS-based CHERI compartment OS for embedded devices without an MMU.

  • CHERIoT: Originally a Microsoft project for running CHERI in IoT/SoC environments without an MMU, only an MMU. Similar in design to CompartOS, but changes CHERI to speed up capability revocation. CHERIoT works around the revocation-by-memory-sweep issue by targeting IoT devices with only a few Gigabytes of memory at most, thus limiting the impact of the asynchronous memory sweeps CHERIoT implements. CHERIoT is a decendant architecture from CHERI.

    SCI semiconductor is in the process of taping out the “ICENI” family of IoT SoCs with CHERIoT IBEX RISC-V cores and “capability aware memory & interconnect”.

Previous Next

© Copyright 2025, Systems Group @ ETH Zürich. Revision 0be91f8b.

Built with Sphinx using a theme provided by Read the Docs.